Register–memory architecture
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In computer engineering, a register–memory architecture is an instruction set architecture that allows operations to be performed on (or from) memory, as well as registers.[1] If the architecture allows all operands to be in memory or in registers, or in combinations, it is called a "register plus memory" architecture.[1]
In a register–memory approach one of the operands for operations such as the ADD operation may be in memory, while the other is in a register. This differs from a load–store architecture (used by RISC designs such as MIPS) in which both operands for an ADD operation must be in registers before the ADD.[1]
An example of register-memory architecture is Intel x86.[1] Examples of register plus memory architecture are:
- IBM System/360 and its successors, which support memory-to-memory fixed-point decimal arithmetic operations, but not binary integer or floating-point arithmetic operations;[2][3][4]
- VAX, which supports memory or register source and destination operands for binary integer and floating-point arithmetic;[5]
- the Motorola 68000 series, which supports integer arithmetic with a memory source or destination, but not with a memory source and destination.[6]
See also
References
- ^ a b c d Michael J. Flynn (1995). Computer architecture: pipelined and parallel processor design. pp. 9–12. ISBN 0867202041.
- ^ IBM System/360 Principles of Operation (PDF). IBM. September 1968. A22-6821-7.
- ^ IBM Enterprise Systems Architecture/370 Principles of Operation (PDF). IBM. August 1988. SA22-7200-0.
- ^ z/Architecture Principles of Operation (PDF). IBM. September 2017. SA22-7832-11.
- ^ VAX Architecture Reference Manual (PDF). Digital Equipment Corporation. 1987. EY-3459E-DP.
- ^ MC68020 32-Bit Microprocessor User's Manual (PDF). Motorola. 1984. MC68020UM[ADI).